The 3D-MAPS Processors
3D-MAPS (3D MAssively Parallel processor with Stacked memory) V1 is a logic+memory 2-tier 3D IC, where the logic die consists of 64 general purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM. This 3D IC is arguably the FIRST many-core general purpose 3D processor developed in academia. This 3D processor achieves up to 64GB/s memory bandwidth while consuming 5W power. This project is led by Prof. Sung Kyu Lim (PI) and Prof. Hsien-Hsin Lee (co-PI) from the Georgia Institute of Technology and Dr. Gabriel Loh (co-PI) from AMD with funding from the US Department of Defense. There have been 20+ students involved in this project working on architecture, programming, CAD tools, circuit and physical design, packaging, board design, and testing. Our collaborators include KAIST, Tezzaron, Amkor Inc, and Board Lab.
The fabrication of this chip is completed in July 2011 using the 130nm GlobalFoundies device technology and 1.2um TSV diameter Tezzaron technology. The packaging is completed in August 2011 by Amkor. 8 parallel applications are developed to demonstrate the bandwidth and power benefit of 3D MAPS processor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5mm x 5mm footprint and 0.8mm thickness.
The core architecture is developed from scratch by our architecture team to benefit from single-cycle access to SRAM. One of the two instructions we issue in one cycle can be memory read/write, so it is possible to access memory at every clock cycle. Our RTL-to-GDSII tool chain is based on commercial tools from Synopsys, Cadence, and Mentor Graphics. Since these tools can only handle 2D ICs, we have developed plug-ins to handle TSVs and 3D stacking. Our work is published at the IEEE International Solid-State Circuits Conference (ISSCC) in 2012 under the title of "3D-MAPS: 3D Massively Parallel Processor with Stacked Memory" (pdf)
In 2013, we taped out 3D-MAPS V2 that features 128 cores and 2GB DRAM stacked in 5 dies. Here are the differences:
Our work is published at the IEEE International Solid-State Circuits Conference (ISSCC) in 2012 under the title of "3D-MAPS: 3D Massively Parallel Processor with Stacked Memory" (pdf)
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