GTCAD Project List

1. Design, Fabrication, and Testing of 3D-MAPS: A Massively Parallel Processor with 3D Stacked Memory (US DOD, 2009-13)
2. 3D Integration of Sub-Threshold Multi-core Co-processor for Ultra Lower Power Computing (NSF, 2009-13)
3. Design of 3D Integrated Heterogeneous Systems (SRC/ICSS, 2011-14)
4. Design for Manufacturability of 3D ICs with Through Silicon Vias (NSF, 2010-13)
5. CAD Tool and Methodology for Reliable 3D-IC Integration (SRC/CADTS, 2012-14)
6. Low Power Computing with Multi-core 3D Processors (SRC/Intel, 2012-14)
7. Design-for-Testing for TSV-based 3D DRAM (Samsung, 2012-13)
8. Low Power and Reliable Designs for Monolithic 3D ICs (Qualcomm, 2012-14)
9. 3D IC Design for Ultra Low Power Wireless Sensor Network (CISS, 2012-)
10. Architecture-aware Power Distribution Network Design for Wide-I/O 3D DRAM (Samsung, 2013-14)

1. Interconnect-centric Physical Design Methodology (GA Yamacraw, 2001-3)
2. Noise Immune On/Off Chip 3-D Routing for High Speed System-On-Package Substrate (NSF, 2002-4)
3. Chip/Package Co-design of Physical Layout for Fast and Reliable System-On-Packages (ACM DAC, 2003-4)
4. Placement and Routing for Polymorphic Computing Architecture (DARPA, 2003-4)
5. NER: Automatic Placedment Algorithms For Quantum-Dot Cellular Automata (NSF, 2004-5)
6. Bringing Low Power Reconfigurable Analog Signal Processing To Embedded Systems (NSF, 2004-7)
7. Mixed Signal Design Tool for System-On-Package (NSF/PRC, 2007-9)
8. High-Performance 3D Microarchitecture Design (SRC/GSRC, 2005-6)
9. High-Performance 3D Microarchitecture Design (SRC/C2S2, 2006-9)
10. CAREER: Physical Design Automation for Fast and Reliable 3D Circuits (NSF, 2006-11)
11. Design for Manufacturing Issues with Through-Silicon-Via (Intel, 2009-11)
12. A Digital Infomedia System - Immersive Technologies on a Hybrid GPU-CPU Platform (KIAT, 2009-12)
13. Co-Optimization and Limit Study of Thermal, Power, Clock, and Signal Distribution Networks in 3D ICs (SRC/IFC, 2007-12)
14. Reliability and Standardization Study for TSV-based Wide I/O DRAM Structures in 3D-IC Integration (SRC/SEMATECH 3D EC, 2011-12)
15. High Density 3D SRAM and Logic Designs with Monolithic 3D Integration (SRC/ICSS, 2011-12)