GTCAD Publication

Publication

BOOK
  1. Sung Kyu Lim, "Practical Problems in VLSI Physical Design Automation," Springer, July 2008 (ISBN: 978-1-4020-6626-9), (buy from Springer, Amazon, or Barnes & Noble)
BOOK CHAPTER
  1. Sung Kyu Lim and Mike Niemier, "Partitioning and Placement for Buildable QCA Circuits," in Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, edited by Sandeep Shukla and Iris Bahar, Spriner, pp 295-316, June 2004. ISBN: 1-4020-8067-0 (pdf)
  2. Young-Joon Lee, Michael Healy, Dae Hyun Kim, and Sung Kyu Lim, "Efficient On-Chip Power, Clock, Thermal, and Signal Delivery for 3D ICs," in Three Dimensional System Integration: IC Stacking Process and Design, edited by Antonis Papanikolaou, Dimitrios Soudris and Riko Radojcic, Springer, 2009.
REFEREED JOURNAL
  1. Jason Cong and Sung Kyu Lim, "Edge Separability based Circuit Clustering With Application to Multi-level Circuit Partitioning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 3, pp. 346-357, 2004. (pdf)
  2. Jason Cong and Sung Kyu Lim, "Retiming-based Timing Analysis With An Application to Mincut-based Global Placement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 12, pp. 1684-1692, 2004. (pdf)
  3. Ramprasad Ravichandran, Sung Kyu Lim, and Mike Niemier, "Automatic Cell Placement for Quantum-dot Cellular Automata," Integration, the VLSI Journal, Vol 38, No. 3, pp. 541-548, 2005. (pdf)
  4. Sung Kyu Lim, Ramprasad Ravichandran, and Mike Niemier, "Partitioning and Placement for Buildable QCA Circuits," ACM Journal on Emerging Technologies in Computing Systems, Vol. 1, No. 1, pp. 50-72, 2005. (pdf)
  5. Sung Kyu Lim, "Physical Design for 3D System-On-Package: Challenges and Opportunities," IEEE Design & Test of Computers, Vol. 22, No. 6, pp. 532-539, 2005. (pdf)
  6. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Multi-objective Module Placement For 3D System-On-Package," IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 5, pp. 553-557, 2006. (pdf)
  7. Peter Sassone and Sung Kyu Lim, "Traffic: A Novel Geometric Algorithm For Fast Wire-Optimized Floorplanning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 6, pp. 1075-1086, 2006. (pdf)
  8. Mongkol Ekpanyapong, Jacob Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, and Sung Kyu Lim, "Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 7, pp. 1289-1300, 2006. (pdf)
  9. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, and David V. Anderson, "Placement for Large-scale Floating-Gate Field Programable Analog Arrays," IEEE Transactions on Very Large Scale Integration Systems, Vol. 14, No. 8, pp. 906-910, 2006. (pdf)
  10. Jacob Minz, Eric Wong, Mohit Pathak, and Sung Kyu Lim, "Placement and Routing for 3D System-On-Package Designs," IEEE Transactions on Components and Packaging Technologies, Vol. 29, No. 3, pp. 644-657, 2006. (pdf)
  11. Jacob Minz and Sung Kyu Lim, "Block-level 3D Global Routing With an Application to 3D Packaging," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 10, pp. 2248-2257, 2006. (pdf)
  12. Wook-Jin Chung, Brian Smith, and Sung Kyu Lim, "Node Duplication and Routing Algorithms for Quantum-dot Cellular Automata Circuits," IEE Proceedings on Circuits, Devices & Systems, Vol. 153, No. 5, pp. 497-505, 2006. (pdf)
  13. Mongkol Ekpanyapong, Michael Healy, and Sung Kyu Lim, "Profile-Driven Instruction Mapping for Dataflow Architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 12, pp. 3017-3025, 2006. (pdf)
  14. Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, and Gabriel H. Loh, "Multi-Objective Microarchitectural Floorplanning For 2D And 3D ICs," IEEE Transactions on Computer-Aided Design of Integrated Ciruits and Systems, Vol. 26, No. 1, pp. 38-52, 2007. (pdf)
  15. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 11, pp. 2023-2034, 2007. (pdf)
  16. Jacob Minz, Somaskanda Thyagaraja, and Sung Kyu Lim, "Optical Routing for 3D System-On-Package," IEEE Transactions on Components and Packaging Technologies, Vol. 30, No. 4, pp. 805-812, 2007. (pdf)
  17. Faik Baskaya, David V. Anderson, and Sung Kyu Lim, "Net Sensitivity Based Optimization of Large-scale Field Programmable Analog Array (FPAA) Placement and Routing", IEEE Transactions on Circuits and Systems II, Vol. 56, No. 7, pp. 565-569, 2009. (pdf)
  18. Mohit Pathak and Sung Kyu Lim, "Performance and Thermal-aware Steiner Routing for 3D Stacked ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 9, pp. 1373-1386, 2009. (pdf)
  19. Yoon Jo Kim, Yogendra K. Joshi, Andrei G. Fedorov, Young-Joon Lee, and Sung Kyu Lim, "Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional IC with Non-Uniform Heat Flux", ASME Journal of Heat Transfer.
REFEREED CONFERENCE
  1. Jason Cong, Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, and Dongmin Xu, "Large Scale Circuit Partitioning With Loose/Stable Net Removal and Signal Flow Based Clustering," IEEE International Conference on Computer-Aided Design, pp. 441-446, 1997. (pdf)
  2. Jason Cong and Sung Kyu Lim, "Multiway Partitioning With Pairwise Movement," IEEE International Conference on Computer-Aided Design, pp. 512-516, 1998. (pdf)
  3. Maogang Wang, Sung Kyu Lim, Jason Cong, and Majid Sarrafzadeh, "Multi-way Partitioning Using Bi-partition Heuristics," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 667-672, 2000. (pdf)
  4. Jason Cong and Sung Kyu Lim, "Performance Driven Multiway Partitioning," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 441-446, 2000. (pdf)
  5. Jason Cong and Sung Kyu Lim, "Edge Separability based Circuit Clustering With Application to Circuit Partitioning," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 429-434, 2000. (pdf)
  6. Jason Cong, Sung Kyu Lim, and Chang Wu, "Performance Driven Multi-level and Multiway Partitioning With Retiming," ACM Design Automation Conference, pp. 274-279, 2000. (pdf)
  7. Jason Cong and Sung Kyu Lim, "Physical Planning with Retiming," IEEE International Conference on Computer-Aided Design, pp. 2-7, 2000. (pdf)
  8. Peter Sassone and Sung Kyu Lim, "A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning," IEEE International Conference on Computer-Aided Design, pp. 74-80, 2003. (pdf)
  9. Jacob Minz and Sung Kyu Lim, "Layer Assignment for System on Packages," ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 31-37, 2004. (pdf)
  10. Mongkol Ekpanyapong and Sung Kyu Lim, "Performance-driven Global Placement via Adaptive Network Characterization," ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 137-142, 2004. (pdf)
  11. Jacob Minz, Mohit Pathak, and Sung Kyu Lim, "Net and Pin Distribution for 3D Package Global Routing," Design, Automation and Test in Europe, pp. 1410-1411, 2004. (pdf)
  12. Ramprasad Ravichandran, Jacob Minz, Mohit Pathak, Siddharth Easwar, and Sung Kyu Lim, "Physical Layout Automation for System-On-Packages," IEEE Electronic Components and Technology Conference, pp. 41-48, 2004. (pdf)
  13. Mongkol Ekpanyapong, Karthik Balakrishnan, Vidit Nanda, and Sung Kyu Lim, "Simultaneous Delay and Power Optimization for Multi-level Partitioning and Floorplanning with Retiming," IEEE International Symposium on Circuits and Systems, pp. 57-60, 2004. (pdf)
  14. Pun Hang Shiu, Ramprasad Ravichandran, Siddharth Easwar, and Sung Kyu Lim, "Multi-layer Floorplanning for Reliable System-on-Package," IEEE International Symposium on Circuits and Systems, pp. 69-72, 2004. (pdf)
  15. Ramprasad Ravichandran, Nihal Ladiwala, Jean Nguyen, Mike Niemier, and Sung Kyu Lim, "Automatic Cell Placement for Quantum-dot Cellular Automata," ACM Great Lake Symposium on VLSI, pp. 332-337, 2004. (pdf)
  16. Mongkol Ekpanyapong, Jacob Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, and Sung Kyu Lim, "Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design," ACM Design Automation Conference, pp. 634-639, 2004. (pdf)
  17. Jacob Minz, Sung Kyu Lim, Jinwoo Choi, and Madhavan Swaminathan, "Module Placement for Power Supply Noise and Wire Congestion Avoidance in 3D Packaging," IEEE Electrical Performance of Electronic Packaging, pp. 123-126, 2004. (pdf)
  18. Jacob Minz and Sung Kyu Lim, "A Global Router for System-on-Package Targeting Layer and Crosstalk Minimization," IEEE Electrical Performance of Electronic Packaging, pp. 99-102, 2004. (pdf)
  19. Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, and Sung Kyu Lim, "Wire Congestion And Thermal Aware 3D Global Placement," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 1131-1134, 2005. (pdf)
  20. Ramprasad Ravichandran, Mike Niemier, and Sung Kyu Lim, "Partitioning and Placement for Buildable QCA Circuits," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 424-427, 2005. (pdf)
  21. Mongkol Ekpanyapong, Michael Healy, and Sung Kyu Lim, "Placement for Configurable Dataflow Architecture," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 1127-1130, 2005. (pdf)
  22. Jacob Minz, Eric Wong, and Sung Kyu Lim, "Thermal and Crosstalk-Aware Physical Design For 3D System-On-Package," IEEE Electronic Components and Technology Conference, pp. 824-831, 2005. (pdf)
  23. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson Hall, and David V. Anderson, "Mapping Algorithm for Large-scale Field Programmable Analog Array," ACM International Symposium on Physical Design, p152-158, 2005. (pdf)
  24. Mongkol Ekpanyapong, Sung Kyu Lim, Chinnakrishnan Ballapuram, and Hsien-Hsin S. Lee, "Wire-driven Microarchitectural Design Space Exploration," IEEE International Symposium on Circuits and Systems, pp. 1867-1870, 2005. (pdf)
  25. Brian Smith and Sung Kyu Lim, "QCA Channel Routing with Wire Crossing Minimization," ACM Great Lake Symposium on VLSI, pp. 217-220, 2005. (pdf)
  26. Jacob Minz, Sung Kyu Lim, and Cheng-Kok Koh, "3D Module Placement for Congestion and Power Noise Reduction," ACM Great Lake Symposium on VLSI, pp. 458-461, 2005. (pdf)
  27. Wook Jin Chung, Brian Smith, and Sung Kyu Lim, "QCA Physical Design With Crossing Minimization," IEEE Conference on Nanotechnology, pp. 262-265, 2005. (pdf)
  28. Michael Healy, Mongkol Ekpanyapong, and Sung Kyu Lim, "MILP-based Placement and Routing for Dataflow Architecture," International Conference on Field Programmable Logic and Applications, pp. 71-76, 2005. (pdf)
  29. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, and David Anderson, "Hierarchical Placement for Large-scale FPAA," International Conference on Field Programmable Logic and Applications, pp. 421-426, 2005. (pdf)
  30. Jacob Minz, Eric Wong, and Sung Kyu Lim, "Reliability-aware Floorplanning for 3D Circuits," IEEE International SOC Conference, pp. 81-82, 2005. (pdf)
  31. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Power Noise-aware 3D Floorplanning for System-On-Package," IEEE Electrical Performance of Electronic Packaging, pp. 259-262, 2005. (pdf)
  32. Mongkol Ekpanyapong, Thaisiri Watewai, and Sung Kyu Lim, "Statistical Bellman-Ford Algorithm With An Application to Statistical Retiming," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 959-964, 2006. (pdf)
  33. Eric Wong and Sung Kyu Lim, "3D Floorplanning with Thermal Vias," Design, Automation and Test in Europe, pp. 878-883, 2006. (pdf)
  34. Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, and Gabriel H. Loh, "Microarchitectural Floorplanning Under Performance and Temperature Tradeoff," Design, Automation and Test in Europe, pp. 1288-1293, 2006. (pdf)
  35. Jacob Minz, Somaskanda Thyagaraja, and Sung Kyu Lim, "Optical Routing for 3D System-On-Package," Design, Automation and Test in Europe, pp. 337-338, 2006. (pdf)
  36. Mongkol Ekpanyapong and Sung Kyu Lim, "Integrated Retiming and Simultaneous Vdd/Vth Scaling for Total Power Minimization," ACM International Symposium on Physical Design, pp. 142-148, 2006. (pdf), Nominated for Best Paper Award.
  37. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Effective Thermal Via and Decoupling Capacitor Insertion Targeting 3D System-On-Package," IEEE Electronic Components and Technology Conference, pp. 1795-1801, 2006. (pdf)
  38. Eric Wong, Jacob Minz, and Sung Kyu Lim, "Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction," IEEE International Conference on Computer-Aided Design, pp. 395-400, 2006. (pdf)
  39. Fayez Mohamood, Michael Healy, Sung Kyu Lim, and Hsien-Hsin S. Lee, "A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design," ACM/IEEE International Symposium on Microarchitecture, pp. 3-14, 2006. (pdf)
  40. Mongkol Ekpanyapong, Xin Zhao, and Sung Kyu Lim, "An Efficient Computation of Statistically Critical Sequential Paths Under Retiming," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 547-552, 2007. (pdf)
  41. Fayez Mohamood, Michael Healy, Sung Kyu Lim, and Hsien-Hsin S. Lee, "Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling," IEEE/ACM Asia South Pacific Design Automation Conference, pp. 786-791, 2007. (pdf)
  42. Faik Baskaya, Brian Gestner, Chris Twigg, Sung Kyu Lim, David V. Anderson, and Paul Hasler, "Rapid Prototyping of Large-scale Analog Circuits with Field Programmable Analog Array," IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 319-320, 2007. (pdf)
  43. Mohit Pathak, Souvik Mukherkee, Madhavan Swaminathan, Ege Engin, and Sung Kyu Lim, "Placement and Routing of RF Embedded Passive Designs In LCP Substrate", IEEE International Conference on Computer Design, pp. 273-279, 2007. (pdf)
  44. Eric Wong and Sung Kyu Lim, "Whitespace Redistribution For Thermal Via Insertion In 3D Stacked ICs", IEEE International Conference on Computer Design, pp. 267-272, 2007. (pdf)
  45. Mohit Pathak, Satya Vadlamudi, Josh Beavers, and Sung Kyu Lim, "Automatic Layout Generation of RF Embedded Passive Designs", IEEE Electrical Performance of Electronic Packaging, pp. 115-118, 2007. (pdf)
  46. Mohit Pathak and Sung Kyu Lim, "Thermal-aware Steiner Routing for 3D Stacked ICs," IEEE International Conference on Computer-Aided Design, pp. 205-211, 2007. (pdf)
  47. Jacob Minz, Xin Zhao, and Sung Kyu Lim, "Buffered Clock Tree Synthesis for 3D ICs Under Thermal Variations", IEEE/ACM Asia South Pacific Design Automation Conference, pp. 504-509, 2008. (pdf)
  48. Dae Hyun Kim and Sung Kyu Lim, "Bus-Aware Microarchitectural Floorplanning", IEEE/ACM Asia South Pacific Design Automation Conference, pp. 204-208, 2008. (pdf)
  49. Michael Healy, Fayez Mohamood, Hsien-Hsin S. Lee, and Sung Kyu Lim, "A Unified Methodology for Power Supply Noise Reduction in Modern Microarchitecture Design", IEEE/ACM Asia South Pacific Design Automation Conference, pp. 611-616, 2008. (pdf)
  50. Dae Hyun Kim and Sung Kyu Lim, "Global Bus Route Optimization with Application to Microarchitectural Design Exploration", IEEE International Conference on Computer Design, pp. 658-663, 2008. (pdf)
  51. Young-Joon Lee and Sung Kyu Lim, "Co-Optimization of Signal, Power, and Thermal Distribution Networks for 3D ICs", IEEE Symposium on Electrical Design of Advanced Packaging and Systems, pp. 163-166, 2008. (pdf)
  52. Michael Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, and Sung Kyu Lim, "Thermal Optimization in Multi-Granularity Multi-Core Floorplanning", IEEE/ACM Asia South Pacific Design Automation Conference, pp. 43-48, 2009. (pdf)
  53. Ye Tao and Sung Kyu Lim, "Decoupling Capacitor Planning With Analytical Delay Model on RLC Power Grid", Design, Automation and Test in Europe, pp. 839-844, 2009. (pdf)
  54. Young-Joon Lee, Yoon-Jo Kim, Gang Huang, Muhannad Bakir, Yogendra Joshi, Andrei Fedorov, and Sung Kyu Lim, "Co-Design of Signal, Power, and Thermal Distribution Networks for 3D ICs", Design, Automation and Test in Europe, pp. 610-615, 2009. (pdf)
  55. Michael Healy and Sung Kyu Lim, "A Study of Stacking Limit and Scaling in 3D ICs: an Interconnect Perspective", IEEE Electronic Components and Technology Conference, pp. 1213-1220, 2009. (pdf)
  56. Young-Joon Lee and Sung Kyu Lim, "Routing Optimization of Multi-modal Interconnects In 3D ICs", IEEE Electronic Components and Technology Conference, pp. 32-39, 2009. (pdf)
  57. Young-Joon Lee, Mike Healy, and Sung Kyu Lim, "Co-design of Reliable Signal and Power Interconnects in 3D Stacked ICs", IEEE International Interconnect Technology Conference, pp. 56-58, 2009. (pdf)
  58. Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim, "TSV-aware Interconnect Length and Power Prediction for 3D Stacked ICs", IEEE International Interconnect Technology Conference, pp. 26-28, 2009. (pdf)
  59. Yoon Jo Kim, Yogendra K. Joshi, Andrei G. Fedorov, Young-Joon Lee, and Sung Kyu Lim, "Thermal Characterization of Interlayer Microfluidic Cooling of Three-Dimensional IC with Non-Uniform Heat Flux", ASME Conference on Nanochannels, Microchannels and Minichannels, 2009
  60. Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim, "Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs", ACM/IEEE International Workshop on System Level Interconnect Prediction, 2009 (pdf)
  61. Jeremy Tolbert, Xin Zhao, Saibal Mukhopadhyay, and Sung Kyu Lim, "Slew-Aware Clock Tree Design For Reliable Subthreshold Circuits", IEEE International Symposium on Low Power Electronics and Design, 2009
  62. Faik Baskaya, David V. Anderson, Paul Hasler, and Sung Kyu Lim, "A Generic Reconfigurable Array Specification and Programming Environment (GRASPER)", IEEE European Conference on Circuit Theory & Design, 2009
  63. Young-Joon Lee, Rohan Goel, and Sung Kyu Lim, "Multi-functional Interconnect Co-optimization for Fast and Reliable 3D Stacked ICs", IEEE International Conference on Computer-Aided Design, 2009. (pdf)
  64. Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim, "A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout", IEEE International Conference on Computer-Aided Design, 2009. (pdf)
  65. Xin Zhao, Dean Lewis, Hsien-Hsin S. Lee, and Sung Kyu Lim, "Pre-bond Testable Low-Power Clock Tree Design for 3D Stacked ICs", IEEE International Conference on Computer-Aided Design, 2009. Nominated for Best Paper Award. (pdf)
  66. Krit Athikulwongse, Xin Zhao, and Sung Kyu Lim, "Buffered Clock Tree Sizing for Skew Minimization Under Power and Thermal Budgets", IEEE/ACM Asia South Pacific Design Automation Conference, 2010.
  67. Xin Zhao and Sung Kyu Lim, "Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) Based 3D ICs", IEEE/ACM Asia South Pacific Design Automation Conference, 2010.